This invention relates generally to improved control circuitry for a counter circuit formed of a plurality of identical bit cells in which each bit cell is fabricated with a smaller number of components than has been traditionally available.
As is generally well known in the art, one of the most common ways to synchronize events occurring in digital logic circuitry is achieved by utilizing conventional counter circuits. These counter circuits are typically adapted to count up to a certain number of clock pulses. Further, such counter circuits may be operated on straight binary counting codes or any other suitable code arrangement. The number of counter cells or stages required depends upon the desired range of the counter circuit. Each of the counter cells corresponds to one bit of the counter circuit.
In a typical binary counting operation of an up counter, prior to starting the counting circuit, a reset signal is supplied to each of the counter cells so that each bit is initially set to "zero." Thereafter, at each cycle of the clock pulses the counter circuit counts up by one. For example, in the case of a 4-bit counter circuit, when the reset signal is applied, the values of the four bits will be set to 0000. Then, after each cycle of the clock pulses following the reset signal, the values of the four bits will be changed to: 0001, 0010, 0011, and so on.
Many conventional counter circuits employ two-phase clocking signals or pulses, with a carry chain. A counter circuit of this type is described in U.S. Pat. No. 5,175,753, issued to Gaglani, entitled `Counter Cell Including a Latch Circuit, Control Circuit and a Pull-Up Circuit`.
Gaglani discloses a counter cell which includes a latch circuit, a control circuit, and a pull-up circuit. FIG. 1 herein is a schematic circuit diagram of a counter cell as disclosed in Gaglani. The latch circuit stores a binary output signal. The latch circuit is formed of a first clocked half-latch having an input and an output, a second clocked half-latch having its input connected to the output of the first clocked half-latch and an output, and an inverter having its input connected to the output of the second clocked half-latch and its output connected to the input of the first clocked half-latch. The first clocked half-latch includes N2, INV3, and INV2 of FIG. 1. The second clocked half-latch includes N3, INV4, and INV5 of FIG. 1. The inverter portion of the half-latch is shown as INV1 in FIG. 1. The first clock phase signal, PH1, is input to the gate of transistor N2, and the second clock phase signal, PH2, is input to the gate of transistor N3. The first clocked half-latch is responsive to a first clock phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch is responsive to a second clock phase signal for transferring the binary output signal from its input to its output.
The control circuit is responsive to an input complement signal ICMPL for selectively passing the first clock phase signal to the first clocked half-latch to permit toggling the state of the binary output signal OUT. The pull-up circuit is responsive to the binary output signal OUT and the input complement signal ICMPL for generating an output complement signal OCMPL. The logic value of the output complement signal OCMPL is maintained at a high logic level when the binary output signal OUT is at a low logic level.
The control circuit as disclosed in Gaglani will now be described in detail, with references made to FIG. 1. The control circuit includes the discharging transistor N1 and the inhibit transistor P3. When the input complement signal ICMPL is set to a High Value, inhibit transistor P3 is turned off. When ICMPL is set to a Low Value, P3 is turned on. When the first clock phase signal PH1 is low, the inverted first clock phase signal PH1L is High. When PH1L is High, discharging transistor N1 is turned on. The effect of transistors P3 and N1 is to apply a high voltage to the gate of transistor N2, thereby enabling the first clocked half-latch only when ICMPL is low and PH1 is High. In all other cases, the potential applied at the gate of N2 is low, and so N2 is in the cutoff state. When N2 is in the cutoff state, the first clocked half-latch is not enabled, and a signal does not pass from the source of N2 to the drain of N2. When the first clocked half-latch is enabled, N2 is conductive and a signal passes from the source of N2 to the drain of N2.
FIG. 2 is a block diagram of a 4-bit counter circuit using counter circuits of Gaglani. All counter cells except the least significant bit counter cell 12 require an inverted first clock phase signal PH1L as an input for the control circuit. This requires an inverter T4 on the first clock phase PH1 input in order to create the inverted first clock phase PH1L that is applied to input I4 of counter 14-1, 14-2 and 14-3.
A plurality of counter cells can be arranged to form an N-bit up-counter, similar to the structure of the 4-bit up-counter shown in FIG. 2. According to a counter cell as disclosed in Gaglani, an N-bit binary counter requires 13 transistors in the first cell, 18*(N-2) transistors in the middle cells, and 15 transistors in the last cell. This counter also requires 2 transistors in inverter T3, 2 transistors in inverter TG, and 2 transistors in transmission gate TG (transistor N4 and P4 in FIG. 1). Therefore, the total transistor count for an N-bit counter of the prior art is 18N-2 transistors.
It would therefore be desirable to provide an improved counter circuit which contains a plurality of identical bit cells, each cell being formed with a smaller number of components than has been traditionally required. Further, it also would be expedient to construct each bit cell to be of a regular configuration or structure so as to conform to a repeatable pattern suitable for very large scale integration (VLSI) with high packing density.